This paper presents a technique to enhance in-band mismatch noise reduction of multi-stage second order Dynamic Element Matching (DEM) in multi-level ΔΣ Digital-to-Analog Converters (DACs). The presented technique changes an operational behavior of multi-stage DEM to reduce mismatch noise at in-band frequency. This change improves mismatch noise shaping performance for small amplitude input signals. Simulation result using 2-stage second order DEM and a third order 17-level ΔΣ modulator with 0.5% analog element mismatch shows 3.4 dB dynamic range improvement.

This paper describes a new architecture-based DSP processor, which consists of n n mesh multiprocessor for digital signal processing. A prototype chip, RCDSP9701 has been designed and implemented using a CMOS 0. 6 µm process. This architecture has better performance compare to the traditional microprocessor solution to Digital Signal Processing. The proposed method poses remarkable flexibility compare to ASIC (Application Specified Integrated Circuits) approach for Digital Signal Processing applications. In addition, the proposed architecture is fault tolerant and suitable for parallel computing applications. In this paper, an implementation into a silicon chip of the new architecture is presented to give a better understanding of our work.

This letter presents a 0.5 V low-voltage op-amp in a standard 0.18 µm CMOS process for switched-capacitor circuits. Unlike other two-stage 0.5 V op-amp architectures, this op-amp consists of CMOS inverters that utilize floating voltage sources and forward body bias for obtaining high-speed operation. And two improved common-mode rejection circuits are well combined to achieve low power and chip area reduction. Simulation results indicate that the op-amp has an open-loop gain of 62 dB, and a high unity gain bandwidth of 56 MHz. The power consumption is only 350 µW.

In order to investigate the jitter characteristics of PLLs for practical applications, we have developed a computer simulation program of PLL, which can deal with arbitrary patterns both of data and jitters, as well as a conceivable nonlinearity of the circuit performance. We used a time-domain method, namely, we solved the state equation of a charge pump type PLL with a constant time step. The jitter transfer characteristics of a conventional PLL were calculated for periodic input data patterns with sinusoidal jitters. The result agreed fairly well with the corresponding experiments. And we have revealed that an ordinary PD (Phase Detector), which detects the phase difference between input and VCO signals at only rising edges, shows the folded jitter transfer characteristics at the half of the equivalent frequency of the input signal. This folded jitter characteristics increases the total jitter for long successive '1' or '0' data patterns, because of their low equivalent sampling frequency, and might increase the jitter even for the random data patterns. Based on simulation results, we devised an improved phase detector for PLL having a low jitter characteristics. And we also applied the simulation to an FDD (Frequency Difference Detector) type fast pull-in PLL which we have proposed recently, and obtained that the jitter of it was smaller than that of a conventional PLL by 25% for PRBS (pseudo random bit sequence) NRZ code.

A new inductance extraction technique of spiral inductor from measurement fixture is presented. We propose a scalable expression of parasitic inductance for interconnects, and design consideration of test structure accommodating spiral inductor. The simple expression includes mutual inductance between the interconnects with high accuracy. The formula matches a commercial field solver inductance values within 1.4%. The layout of the test structure to reduce magnetic coupling between the spiral and the interconnects allows us to extract the intrinsic inductance of spiral more accurately. The proposed technique requires neither special fixture used for measurement-based method nor skilled worker for precise extraction with the analytical technique used.

A new architecture-based Dynamically Programmable Arithmetic Array processor (DPAA) is proposed for general purpose Digital Signal Processing applications. Parallelism and pipelining are achieved by using DPAA, which consists of various basic arithmetic blocks connected through a code-division multiple access bus interface. The proposed architecture poses 100% interconnection flexibility because connections are done virtually through code matching instead of physical wire connections. Compared to conventional multiplexing architectures, the proposed interconnection topology consumes less chip area and thus, more arithmetic blocks can be incorporated. A 16-bit prototype chip incorporating 10 multipliers and 40 other arithmetic blocks had been implemented into a 4.5 mm 4.5 mm chip with 0.6 µm CMOS process. DPAA also features its simple programmability, as numerical formula can be used to configure the processor without programming languages or specialized CAD tools.

An ultralow power constant reference current circuit with low temperature dependence for micropower electronic applications is proposed in this paper. This circuit consists of a constant-current subcircuit and a bias-voltage subcircuits, and it compensates for the temperature characteristics of mobility µ, thermal voltage VT, and threshold voltage VTH in such a way that the reference current has small temperature dependence. A SPICE simulation demonstrated that reference current and total power dissipation is 97.7 nA, 1.1 µW, respectively, and the variation in the reference current can be kept very small within 4% in a temperature range from -20 to 100.

A RF front-end chip for a dual-band Global Positioning System (GPS) receiver for L1 and L2 bands is designed using 0.25 µm CMOS technology. All function blocks of the GPS front-end are integrated onto one chip. The low noise amplifier has input matching over a wide frequency range to handle the L1 and L2 bands. This receiver uses a dual-band image-reject mixer with the quadrature mixer sharing a transconductor stage. This configuration enables the RF blocks to be shared with the L1 and L2 bands. The receiver has a chip area of 3.16 mm3.16 mm, and consumes 35 mA at 2.5 V.

A 0.5 V transformer folded-cascode CMOS low-noise amplifier (LNA) is presented. The chip area of the LNA was reduced by coupling the internal inductor with the load inductor, and the effects of the magnetic coupling between these inductors were analyzed. The magnetic coupling reduces the resonance frequency of the input matching network, the peak frequency and magnitude of the gain, and the noise contributions from the common-gate stage to the LNA. A partially-coupled transformer with low magnetic coupling has a small effect on the LNA performance. The LNA with this transformer, fabricated in a 90 nm digital CMOS process, achieved an S11 of -14 dB, NF of 3.9 dB, and voltage gain of 16.8 dB at 4.7 GHz with a power consumption of 1.0 mW at a 0.5 V supply. The chip area of the proposed LNA was 25% smaller than that of the conventional folded-cascode LNA.

Electron transport in bulk Si and MOSFET inversion layers is studied using an ensemble Monte Carlo (EMC) technique coupled with the molecular dynamics (MD) method. The Coulomb interactions among point charges (electrons and negative ions) are directly taken into account in the simulation. It is demonstrated that the static screening of Coulomb interactions is correctly simulated by the EMC/MD method. Furthermore, we calculate the inversion layer mobility in Si MOSFETs, and mobility roll-off near the threshold voltage is observed by the present approach.

An intermediate frequency (IF) variable gain amplifier (VGA) with exponential gain control for a radio receiver is fabricated in 0.25-µm CMOS technology. The techniques to improve the bandwidth and to reduce temperature dependence of gain are described. The complete VGA is composed of two stages of linearized transconductance VGA and three stages of fixed gain amplifier (FGA). The complete VGA provides a continuous 10 dB to 76.5 dB gain control range, an IIP3 of -11.5 dBm and an NF of 15 dB at 40 MHz.

A demodulator for short-range wireless interconnect using ASK/CDMA technique has been developed with 0.25 µm CMOS technology. The fabricated demodulator demonstrates the demodulation of 7.35 Mbps bit rate with 31 spread spectrum code length at 10 GHz carrier frequency.

A new analog correlator circuit is proposed for direct sequence code division multiple access (DS-CDMA) demodulator. The circuit consists of only 16 switches, 4 capacitors and 2 level shifters. Control sequence requires only three clock phases. Simulation with code length of 127 reveals that the proposed circuit has a good ability to cancel off the charge error and dissipates 3.4mW at 128MHz. The circuit had been designed using a 0.6µm CMOS process. The area of 256µm 245µm is estimated to be 9 times smaller compared to other reported equivalent analog correlators.

Hot carrier effects in narrow-channel MOSETs are investigated. With decreasing channel width below 1µm, the ratio of substrate to channel currents show marked increase. By using the newly developed full three-dimensional process/device simulation system, two significant causes of the hot carrier effects are clarified.

Thickness dependence of breakdown properties in control and N2O-Oxynitrided oxides was investigated. Nitrogen atoms piled up at the Si/SiO2 interface increase charge-to-breakdown (QBD) under substrate injection conditions for oxide thickness below 10 nm, while no meaningful improvement is observed above 10 nm. This thickness dependence is explained by the fact that N2O-oxynitridation reduces oxide defects near the Si/SiO2 interface. N2O-oxynitridation of the oxides reduces the number of neutral electron traps due to the chemical reaction of oxide defect with nitrogen atoms. Electron trapping of N2O-oxynitrided oxides is significantly suppressed; the reduction of electron trapping events into neutral electron traps increases QBD under substrate injection. On the other hand, under gate injection, N2O-oxynitrided oxides show low rate of hole trapping during the initial stress period. However, in heavily injected condition, electron trapping is not suppressed, resulting in little improvement of QBD. In addition, the control and N2O-oxynitrided oxides show quite similar dependence of QBD on stress current density, which is related primarily to the carrier transport phenomena (tunneling, traveling, impact ionization and hole injection).

We propose a nonlocal impact ionization model applicable for the drain region where electric field increases exponentially. It is expressed as a function of an electric field and a characteristic length which is determined by a thickness of gate oxide and a source/drain junction depth. An analytical substrate current model for n-MOSFET is also derived from the new nonlocal impact ionization model. The model well explains the reason why the theoretical characteristic length differs from empirical expressions used in a pseudo two-dimensional model for MOSFET's. The nonlocal impact ionization model implemented in a device simulator demonstrates that the new model can predict substrate current correctly in the framework of drift-diffusion model.

We propose an ultra low power watch-dog circuit with the use of MOSFETs operation under subthreshold characteristics. The circuit monitors the amount of the product degradation because the subthreshold current of MOSFET emulates the rate of the general chemical reaction. Its operation was verified with both SPICE simulation and the measurement of the prototype chip. The new circuit embedded in a tag attached to any product could dynamically monitor the degradation regardless of storage conditions.